1. Field of the Invention
The present invention relates to the use of an equalizer algorithm and/or apparatus in a discrete multi-tone transceiver (DMT) and, more particularly, to an adaptive equalizer algorithm and/or apparatus which operates on each bin individually as an alternative to using a time domain equalizer (TEQ) in digital subscriber line (xDSL) transceivers.
2. Related Art
The fast, efficient and error-free transmission of digital information from one point to another has become increasingly important. Many communications systems exist which permit digital information to be transmitted over various types of communication channels, such as wireless channels, fiber-optic channels, and wire line channels.
The present invention will be described in the context of a wire line communications channel, such as a telephone line which utilizes a twisted pair of copper wires. It is noted that the use of the present invention is not limited to wire line systems as those skilled in the art will appreciate from the discussion hereinbelow.
A modem is typically used to transmit and receive digital data over a telephone line. Modems employ a modulator to transmit the digital data over the telephone line and a demodulator to receive digital data from the telephone line. One common modulation technique is known as digital multi-tone modulation which requires a discrete multi-tone transmitter and a discrete multi-tone receiver at each modem in a communication system. Often, those skilled in the art refer to such modems as employing a DMT physical layer modulation technique.
Reference is now made to FIG. 1 which is a block diagram of a conventional DMT communications system 1. The system 1 includes a DMT transmitter 10, a transmission channel 20, and a DMT receiver 30. The DMT transmitter 10 includes a symbol generator 12, an inverse fast Fourier transform (IFFT) modulator 14, and a cyclic prefix generator 16. The DMT transmitter 10 receives an input bit stream b(n) which is fed into the symbol generator 12. The symbol generator 12 produces a signal vector X(k) which is fed into the IFFT modulator 14. X(k) is a complex signal vector (i.e., a signal understood by those skilled in the art to comprise both real and an imaginary components of quadrature amplitude modulation QAM data symbols) formed by mapping pairs of bits of the input bit stream b(n) into a complex data space such that the complex signal vector X(k) has a length of N/2 samples. Symbol generator 12 also augments the complex signal vector X(k) with a complex conjugate (of the N/2 samples) to obtain a conjugate symmetric signal of N samples.
The IFFT modulator 14 performs an N-point inverse fast Fourier transform on the complex signal vector X(k) to obtain the sampled real signal x(n). Since X(k) is a Hermitian type symmetric signal vector, the output of the IFFT modulator 16 is a real signal x(n). The real signal x(n) may be thought of as the summation of a plurality of cosine functions each having a finite length and a different frequency, phase, and amplitude, where these frequencies are multiples of a fundamental frequency. Since each of the cosine functions has a finite duration, x(n) is a varying amplitude discrete signal having a finite duration spanning N samples. Those skilled in the art will appreciate that the frequency spectrum of x(n) may be thought of as a plurality of orthogonal (SINxc2x7X)/(X) functions, each centered at a respective one of the frequencies of the cosine functions of x(n).
Those skilled in the art will appreciate that the transmission channel 20 includes a D/A converter (not shown), transmit filter (not shown), a receive filter (not shown), and an A/D converter (not shown) on either end of a wire loop (not shown).
x(n) is transmitted over the channel 20 to the DMT receiver 30. Since the transmission channel 20 has a non-ideal impulse response h(n), the received signal r(n) will not exactly match x(n). Instead, r(n) will be a function of the convolution of x(n) and h(n). Typically, h(n) will look substantially like the curve shown in FIG. 2. The non-ideal characteristic of h(n) introduces an amount of interference (specifically inter-symbol and inter-channel interference) which should be compensated for in both the DMT transmitter 10 and the DMT. receiver 30.
A common technique in compensating for the non-ideal impulse response of the transmission channel 20 is to introduce a so-called guard band at the beginning of each finite duration signal x(n) to produce xxe2x80x2(n). The cyclic prefix generator 16 performs this function. The guard band is typically formed of the last V samples of x(n) for each DMT symbol. If the length of the impulse response h(n) of the transmission channel 20 is less than or equal to V+1, then the guard band of length V will be sufficient to eliminate the interference cause by the impulse response h(n). The guard band is commonly referred to in the art as a xe2x80x9ccyclic prefixxe2x80x9d (CP).
Unfortunately, the impulse response h(n) of a typical transmission channel 20 may be excessively long, requiring cyclic prefix lengths which substantially reduce the rate at which digital bits are transmitted across the transmission channel 20. The DMT receiver 30, therefore, employs signal processing techniques which effectively shorten the impulse response h(n) of the transmission channel 20, thereby permitting a corresponding reduction in the length of the cyclic prefix required at the DMT transmitter 10.
The DMT receiver 30 includes a time-domain equalizer (TEQ) 32, a windowing circuit 34, a fast Fourier transform (FFT) demodulator 36, and a bit generator 38. The time-domain equalizer 32 is a finite impulse response (FIR) filter designed to compensate for the non-ideal impulse response h(n) of the transmission channel 20. In particular, the time-domain equalizer 32 employs a finite number of coefficients which are calculated to compensate for the non-ideal impulse response of the transmission channel 20. The time domain equalizer 32 operates on the impulse response h(n) of the channel 20 such that the combined impulse response heft(n) of the channel 20 and the time domain equalizer 32 has a maximum of energy within a limited band (or set) of consecutive samples. This may be thought of as xe2x80x9cshorteningxe2x80x9d the effective impulse response of the channel 20. The output of the time domain equalizer is zxe2x80x2(n).
A rectangular windowing circuit 34 is employed to remove the cyclic prefix from zxe2x80x2(n) to obtain z(n). Non-rectangular windowing circuits have also been employed in the prior art to improve frequency spectral containment. The signal z(n) is input into the FFT demodulator 36 (which is understood to include a frequency domain equalizer function) to produce the complex symmetric signal vector X(k). After (i) the complex conjugate portion of the signal vector X(k) is removed, and (ii) compensation of non-rectangular windowing has been accomplished, the bit generator 38 maps the complex signal vector X(k) into an output bit stream b(n), which theoretically matches the input bit stream b(n).
Several algorithms exist for calculating the T coefficients of the time-domain equalizer 32. One such algorithm is referred to as the least squares based pole zero cancellation algorithm, which is discussed in detail in P. J. Melsa, R. Y. Younce and C. E. Rohrs, xe2x80x9cImpulse Response Shortening for Discrete Multitone Transceivers,xe2x80x9d IEEE Trans. On Comm. Vol. 44, No. 12, pp. 1662-71, December 1996. Another such algorithm is referred to as the optimal shortening algorithm which is also discussed in detail in the above referenced IEEE publication. Still another algorithm is referred to as the eigenvector approach using the power method which is discussed in detail in M. Nafie and A. Gatherer, xe2x80x9cTime-Domain Equalizer Training for ADSL,xe2x80x9d Proc. ICC, pp. 1085-1089 (1997). Yet another algorithm is disclosed in U.S. patent application Ser. No. 07/249,530, entitled xe2x80x9cIMPROVED DMT TIME DOMAIN EQUALIZER ALGORITHM, filed Feb. 12, 1999, the entire disclosure of which is hereby incorporated by reference.
Although the above techniques for calculating the coefficients of the time-domain equalizer 32 address the issue of xe2x80x9cshorteningxe2x80x9d the effective impulse response of the transmission channel 20, they do not address the problem of adaptively tracking changes in the transfer function of the communication channel 20 over time and any time variant positioning of narrow band interference sources. Furthermore, these techniques are relatively complex and controllability thereof is non-trivial. Still further, some of these techniques result in an increase in interference due to additive noise coloring in the received signal.
Accordingly, there is a need in the art for an improved DMT communication system which is capable of (i) adaptively compensating for time variations in the communications channel transfer function; (ii) compensating for inter and intra bin interference; and (iii) adaptive notching narrow-band radio frequency interference from the received DMT signal; and (iv) reduced complexity optimal decoding of non-rectangular windowing induced inter-bin (inter subchannel) interference.
In order to overcome the deficiencies in the prior art, the present invention provides an apparatus for receiving a discrete multi-tone (DMT) signal representative of a series of input symbols and including a plurality of orthogonal sinusoidal subchannels of finite length for each input symbol, the apparatus comprising: a plurality of delay circuits, each operable to receive the DMT signal and produce a delayed DMT signal; a plurality of windowing circuits, each operable to receive a respective one of the delayed DMT signals and produce a windowed DMT signal; at least one finite duration fast Fourier transform (FFT) circuit, operable to receive the windowed DMT signals and produce respective complex signals representing a plurality of bins corresponding to the subchannels of the DMT signal in time shared fashion; a plurality of multiplier circuits, each operable to produce a product of (i) a complex factor for compensating for a respective phase shift introduced by a corresponding one of the delay circuits, an equalizer circuit operable to receive the products from the plurality of multiplier circuits and produce a partial response signaling (PRS) coded signal; and a PRS decoder operable to receive the PRS coded signal and produce output symbols representative of the input symbols.
Preferably, the apparatus further comprises 1, 2, 3, through (Kxe2x88x921) delay circuits, wherein one of the windowing circuits is operable to receive the DMT signal which has not been delayed. More particularly, it is preferred that the DMT signal includes N samples spaced To/N seconds apart representing each input symbol, and each delay circuit delays the DMT signal by a respective multiple of 1, 2, 3, through (Kxe2x88x921) times To/K. Alternatively, the DMT signal may include N samples representing each input symbol and V samples representing a cyclic prefix for each input symbol, the N+V samples being spaced Ts/(N+V) seconds apart, and each delay circuit delays the DMT signal by a respective multiple of 1, 2, 3, through (Kxe2x88x921) times Ts/K.
It is preferred that each of the windowing circuits is a Hanning type window.
It is also preferred that active bins of the FFT circuit are input into respective ones of the multiplier circuits and multiplied by a respective one of the complex factors.
Preferably, the equalizer circuit is operable to sequentially receive k-th products from the multiplier circuits of k-th bins to produce an over sampled signal for a k-th one of the subchannels of the DMT signal. The equalizer circuit may be a linear circuit comprising: a finite impulse response feed forward filter (FFF) having K*L aggregated taps and being operable to receive the over sampled signal and produce a forward filtered signal; a multiplier circuit operable to produce the PRS coded signal by multiplying (i) a complex factor for compensating for a cyclic prefix of each symbol, and (ii) the forward filtered signal; a PRS slicer circuit operable to receive the PRS coded signal and produce PRS signal levels for each bin; and a first summing circuit operable to produce an error signal corresponding to a difference of the PRS coded signal and the PRS signal levels, the error signal being used to adaptively produce coefficients for the taps of the FFF.
The equalizer circuit preferably also includes an adaptive circuit operable to produce FFF coefficients during a training phase, the adaptive circuit comprising a PRS coding circuit operable to receive a training signal of known symbols to produce a training PRS coded signal, wherein the summing circuit is operable to produce an error signal corresponding to a difference of the training PRS coded signal and the PRS coded signal at the output of the FFF, the error signal being used to adaptively produce the FFF coefficients for the taps of the FFF. It is most preferred that the adaptive circuit is operable to produce the FFF coefficients intermittently.
The equalizer circuit may alternatively be a non-linear circuit comprising: a finite impulse response feed forward filter (FFF) having a plurality of aggregated taps and being operable to receive the over sampled signal and produce a forward filtered signal; a multiplier circuit operable to produce a phase shifted signal by multiplying (i) a complex factor for compensating for a cyclic prefix of each symbol, and (ii) the forward filtered signal; a first summing circuit operable to produce a difference signal corresponding to a difference of the phase shifted signal and a feedback filtered signal; a PRS slicer circuit operable to receive the difference signal and produce PRS signal levels for each bin; a finite impulse response feed back filter (FBF) having a plurality of aggregated taps and being operable to receive the PRS signal levels and produce the feedback filtered signal; and a second summing circuit operable to produce an error signal corresponding to a difference of the difference signal and the PRS signal levels, the error signal being used to adaptively produce the coefficients for the taps of the FFF and the FBF.
The equalizer circuit also preferably includes an adaptive circuit operable to produce FFF coefficients and FBF coefficients during a training phase, the adaptive circuit comprising a PRS coding circuit operable to receive a training signal of known symbols to produce a training PRS coded signal, wherein the second summing circuit is operable to produce an error signal corresponding to a difference of the difference signal and the PRS coded signal, the error signal being used to adaptively produce the FFF coefficients for the taps of the FFF and the FBF coefficients for the taps of the FBF.
The equalizer circuit may alternatively be a non-linear circuit which includes decision feedback, the equalizer circuit comprising: a finite impulse response feed forward filter (FFF) having a plurality of aggregated taps and being operable to receive the over sampled signal and produce a forward filtered signal; a multiplier circuit operable to produce a phase shifted signal by multiplying (i) a complex factor for compensating for a cyclic prefix of each symbol, and (ii) the forward filtered signal; a first summing circuit operable to produce a difference signal corresponding to a difference of the phase shifted signal and an aggregate feedback filtered signal; a PRS slicer circuit operable to receive the difference signal and produce PRS signal levels for each bin; a first finite impulse response feed back filter (FBF) having a plurality of aggregated taps and being operable to receive the PRS signal levels for a k-th bin and produce a first feedback filtered signal; a second FBF having a plurality of aggregated taps and being operable to receive the PRS signal levels for a (kxe2x88x921)th bin and produce a second feedback filtered signal; a third FBF having a plurality of aggregated taps and being operable to receive the PRS signal levels for a (k+1)th bin and produce a third feedback filtered signal; a second summing circuit operable to produce the aggregate filtered feedback signal by summing the first, second, and third feedback filtered signals; and a third summing circuit operable to produce an error signal corresponding to a difference of the difference signal and the PRS signal levels, the error signal being used to adaptively produce the coefficients for the taps of the FFF and the first, second, and third FBFs.
It is most preferred that the PRS decoder includes at least one of (i) a decision feedback decoder; (ii) a maximum likelihood sequence estimator; and (iii) a Viterbi decoder.
According to another aspect of the present invention, the invention provides an apparatus for receiving a discrete multi-tone (DMT) signal representative of a series of input symbols and including a plurality of orthogonal sinusoidal subchannels of finite length for each input symbol, the apparatus comprising: a plurality of delay circuits, each operable to receive the DMT signal and produce a delayed DMT signal; at least one (time-shared) finite length fast Fourier transform (FFT) circuit, operable to receive the delayed DMT signals and produce respective complex signals representing a plurality of bins corresponding to the subchannels of the DMT signal; a plurality of frequency domain windowing circuits, each operable to receive a respective one of the complex signals and produce a windowed complex signal; a plurality of multiplier circuits, each operable to produce a product of (i) a complex factor for compensating for a respective delay circuit, and (ii) a respective one of the windowed complex signals; an equalizer circuit operable to receive the products from the plurality of multiplier circuits and produce a partial response signaling (PRS) coded signal; and a PRS decoder operable to receive the PRS coded signal and produce output symbols representative of the input symbols.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.